(Nasdaq: SNPS) today announced that Renesas Electronics Corporation has deployed Synopsys’ Fusion Compiler™ RTL-to-GDSII implementation solution for its high-performance automotive system-on-chips (SoCs) and mission-critical microcontrollers (MCUs) to accelerate broad market access to next-generation automotive designs. Fusion Compiler delivered optimal timing and power quality-of-results (QoR), smaller area, and faster time-to-results (TTR) on multiple production designs during Renesas’ extensive validation process. After successfully realizing the compelling benefits of the solution on initial designs, Renesas is broadly deploying Fusion Compiler to extend the benefits to its automotive design teams. Renesas will join other market-leading semiconductor companies to share its experiences with Fusion Compiler at the Lunch-and-Learn Panel at the Synopsys Users Group () Silicon Valley Conference at the Santa Clara Convention Center on March 21, 2019.
“Fusion Compiler was unveiled last November, setting a new bar for power, performance, area, and designer productivity,” said Shankar Krishnamoorthy, senior vice president of engineering, Synopsys Design Group. “Seeing our leading-edge customers across multiple market segments quickly realize the benefits of our solution and achieve rapid deployment is a strong affirmation of the readiness and unique value of this innovative RTL-to-GDSII product. Renesas’ broad adoption of Fusion Compiler is a significant endorsement, and we are committed to continue collaborating with Renesas and other market leaders in the design of state-of-the-art chips for automotive and other applications.”
“As the leading supplier of automotive SoC and microcontroller products, Renesas is pushing the limits of power and performance efficiency to continue to deliver highly-differentiated products for the next generation of connected and autonomous cars,” said Tatsuji Kagatani, vice president, Shared R&D Division 2, Broad-based Solution Business Unit, Renesas Electronics Corporation. “Synopsys’ Fusion Compiler consistently delivered superior power, performance, and full-flow productivity on our production tapeout designs. We are confident that this new Synopsys product will continue to be instrumental to achieving our ambitious goals and help us accelerate innovations for our advanced products.”
Fusion Compiler is uniquely architected to enable design teams to achieve the optimal levels of power, performance, and area (PPA) in the most convergent manner to ensure the fastest and most predictable TTR. Built using a single, highly-scalable data model, and based around an analysis backbone that leverages technology from the industry’s golden-signoff analysis tools, Fusion Compiler guarantees that these critical PPA metrics are optimized efficiently and effectively throughout the full RTL-to-GDSII design flow. Fusion Compiler delivers best-in-class PPA through a highly-leveraged optimization framework, resulting in a fully-unified physical synthesis and optimization methodology where industry-leading technologies can be deployed at any point throughout the flow for maximum effect. This groundbreaking approach delivers up to 20 percent better timing, 10-15 percent better total power, and up to 5 percent better area compared to using a traditional combination of front- and back-end tools. Additionally, Fusion Compiler’s novel synthesis engine has been further enhanced to support innovative hierarchical design flows and global design planning methodologies to provide significant productivity gains.